A sense amplifier which is arranged in a DRAM environment (DRAM=Dynamic Random Access Memory) is illustrated within the area of the dashed line A in FIG. 1. Bit line signals IBLT and IBLC are supplied via bit lines in the sense amplifier.
The conventional cross-coupled sense amplifier illustrated in FIG. 1 is shown in more detail in the split—sense amplifier—arrangement in FIG. 2.
FIG. 3 shows the associated timing diagrams, with FIG. 3(a) showing the bit line signals IBLC (dashed line) and IBLT (dashed-dotted line) for sensing with precharging, as a function of time. The time axis is, by way of example, subdivided into a time period from 0 to 80 ns (nanoseconds).
FIG. 3(b) shows the word line signal WL (dashed line) as well as two signals which are input (EQLR) to a downstream amplifier group, as well as a signal EQLL which is supplied to an upstream amplifier group. At the start of the measuring cycle, the signals EQLR and MUX1 (see FIG. 1) are not passed on.
In addition, the signal MUXr which is supplied to a transistor pair downstream from the sense amplifier in FIG. 1, is driven from an intermediate level VINP to a raised level VPP. In parallel with this, the level on the word line WL is raised such that the cell capacitor of a memory cell array (DRAM) can be read.
When a “0” is sensed, as is described here, the voltage level on the bit line IBLT is reduced after a charge transfer. Sensing by the sensor amplifier is then started by setting a signal SAN which is arranged at the junction point between the transistors N1 and N2, to a low level and a signal SAP, which is arranged at the junction point between the transistors P1 and P2 to a high level.
In this way, the transistors N1, N2 and P1, P2 start to act as a cross-coupled inverter or as a switching device, as a result of which the voltage IBLT is amplified to zero, and the voltage IBLC is amplified to VBLH.
At the end of the cycle, as is illustrated in the timing diagram in FIG. 3(b), the word line level WL is reduced (in this example at about 52 ns). All the other voltages are then returned to the initial level, which leads to automatic precharging to the initial level VBLH/2.
The advantages of this conventional method are that all that is required for sensing and amplification in the sense amplifier that is annotated A in FIG. 1 is to provide a charge equivalent to the capacitance of the bit line, multiplied by VBLH/2.
One major disadvantage of this conventional method is that the voltage VBLH cannot be reduced sufficiently, as is required for future generations of DRAM sense amplifiers. When a “0” is sensed, the transistor N1 has to discharge the line IBLT. In contrast, the gate/source voltage of the transistor N1 is often even less than the voltage level VBLH/2.
The source level of the transistor N1, that is to say the level SAN, is thus drawn to “0”, and the IBLC level is reduced slightly from the precharging level VBLH/2 as a result of the line coupling capacitance between IBLT and IBLC. In consequence, the lower the setting of the level VBLH, the more slowly the sensing and amplification are carried out in the sense amplifier. This cannot be tolerated in circuit arrangements, since the sense speed determines the minimum time between activation of a row and the capability to read from this row for the first time. This time is specified as tRCD in the data sheet.
Conventional solutions to this problem comprise reduction of the threshold voltages for the relevant devices. However, the level to which a threshold voltage can be reduced is restricted by the parallel current through the devices when signals on the bit lines are amplified.
In this situation, the entire level VBLH is applied between the source SAN and drain (for example IBLC in FIG. 2). Since, however, thousands of bit lines have to be set or reset in parallel in conventional memory apparatuses (DRAMs), only an extremely small parallel current or leakage current can be allowed.
Any reduction in VBLH by reducing the threshold voltage (Vth) is thus subject to tight limits, so that VBLH cannot be reduced effectively.
A further proposal that has been made is to operate SAN negatively. This is subject to the disadvantage that the SAN driver is highly complicated, that is to say it has to provide three voltage levels, that is to say VBLH/2, ground and a negative value.
Furthermore, the FET junction of the transistors are biased in a forward direction when SAN is driven negatively.
A further proposal to solve the above problem comprises the provision of ground-level precharging rather than carrying out VBLH/2 precharging. This results in the disadvantage of an increased power consumption, since sensing and amplification now require a charge which is governed by the capacitance of the bit line multiplied by VBLH (previously: multiplied by VBLH/2).
A further substantial disadvantage of conventional array architectures is that ground-level precharging is no longer possible because an adequate current must be ensured when the array transistor is in the off state, with WO being biased negatively with respect to the bit line when it is not selected. Ground-level precharging requires, however, that the precharging level should not be supplied via ground. A high leakage current or a high parallel current thus disadvantageously results in the case of a negatively biased bit line WL with a grounded bit line.
One object of the present invention is thus to provide a sense amplifier apparatus and a method for sensing and amplification of bit line signals, in which an operating voltage can be reduced, while overcoming the disadvantageous effects of sense amplifier apparatuses according to the prior art.